Research analysis · PMAD and wiring

A 175,000-parameter watchdog for a 400 Hz power bus

An IEEE Transactions on Aerospace and Electronic Systems paper demonstrates that a deliberately small residual network can classify 21 electrical fault and power quality conditions on a 400 Hz aircraft power bus at 96.94% test accuracy, then runs the same network, quantized to 8 bits, on a Xilinx FPGA at 6.90 ms mean latency per record with 95.87% accuracy. The entire evaluation lives inside a simulator. The result is genuinely useful engineering evidence about the shape of the monitoring stack, and it is not yet evidence about any real power bus.

Source: Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems, IEEE Transactions on Aerospace and Electronic Systems, accepted September 2, 2026; arXiv:2609.10479 [eess.SP], September 9, 2026. Primary source. Read: the complete 22-page author manuscript PDF, retrieved from arXiv, including Tables I through VI and Figures 1 through 16.

What the work claims

Guzman, Babiceanu and Pekoz claim three things. First, that data-driven classification of faults and power quality disturbances in 400 Hz aerospace power systems, a frequency regime most machine-learning power work ignores in favor of 50 or 60 Hz grids, is feasible at high accuracy across many classes: their Compact ResNet achieves 96.94% software test accuracy across 21 classes with only 175,685 parameters, within 0.35 percentage points of the best model they tested, a 1D-CNN with 8,338,709 parameters (Table III)1. Second, that the model survives quantization and real hardware: after 8-bit quantization of weights and activations and deployment through the MATLAB DL HDL Toolbox on a Xilinx Zynq UltraScale+ MPSoC ZCU102 board, it holds 95.87% accuracy, a 1.07 percentage point drop, with a measured mean on-board latency of 6.90 ms and worst-case 14.40 ms per input record (Table VI)1. Third, that the accelerator fits alongside other functions on one FPGA: post-synthesis utilization is 391 of 2,520 DSP slices (15.52%), 581 of 912 Block RAM (63.71%), and 256,992 of 274,080 CLB LUTs (93.77%) (Table V)1.

The authors bound their own claim in a way this reading will honor: because data augmentation and GAN synthesis were applied before the train, validation and test split, the reported metrics are, in their words, held-out-sample evaluation over stochastic realizations drawn from the same simulated data-generation process, not a parent-waveform-disjoint or independent operating-campaign validation1. Everything in this article treats the numbers accordingly.

How it works

The power system under test is a high-fidelity simulation model inspired by the Boeing 787 electrical architecture: a 250 kVA three-phase synchronous generator feeds a 230 V AC main busbar at 400 Hz, a transformer steps down to a 115 V auxiliary AC busbar, and two transformer rectifier units produce 28 V and 270 V DC buses, with contactors and breakers handling distribution (Fig. 1)1. Waveforms are recorded at 33.3 kHz. Twenty-one classes were simulated (Table I): normal operation, start-up switching transients, eight power quality disturbances from voltage sag through flicker, two combined disturbances, and nine hardware faults spanning generator open and short circuits, transformer faults, TRU open circuits, and 28 V busbar faults.

The dataset construction is where most of the engineering sits. Each class holds 3,500 samples of 1,000 points each (73,500 total), of which only 100 per class are raw simulation output; 3,000 per class come from signal-processing augmentation (scaling, noise injection, frequency warping, jitter, polarity inversion) and 400 per class from class-specific generative adversarial networks trained for 50 epochs each (Table II)1. The authors validate the GAN output three ways: power spectral density mean squared error on the order of 10-9, dynamic time warping distance tracking the real-to-real baseline, and UMAP projections showing synthetic samples on the same manifolds as real ones (Figs. 4 to 6)1. Time-domain signals feed 1D architectures; short-time Fourier transform spectrograms (33 by 30 arrays from a 64-sample window with 32-sample overlap) feed the 2D architectures, including the Compact ResNet, which stacks three residual layers with 16, 32 and 64 channels (Fig. 7)1. On the FPGA, the quantized network executes on a dedicated DL processor IP core over AXI4, with external DDR for weights and activations and a profiler module for timing; latency was measured by timing 1,000-sample batches and subtracting the independently measured host round-trip delay using a passthrough kernel1. The measurement boundary of the 6.90 ms figure is the neural accelerator core only: the STFT front end ran on the host computer, and integrating data acquisition, STFT and inference on one chip is explicitly future work.

The strongest case for it

The accuracy-versus-size trade is the real result. VGG16 needed 138,424,765 parameters for 96.55%; the Compact ResNet gets 96.94% with 175,685, better accuracy at roughly one seven-hundredth the parameter count (Table III)1. For a resource-constrained platform this is decisive, and it matches what spacecraft power electronics engineers already know: the marginal 0.35 points of accuracy from the 8-million-parameter 1D-CNN buy nothing a bus manager can use, while every DSP slice and LUT matters when the same device must also close control loops. The 8-bit quantization story is equally practical: a 1.07 point drop to 95.87% on hardware is within the noise of most protection-engineering tolerances, and the tight latency bound (worst case 14.40 ms, observed on class 11) is the property a safety case actually needs, because a watchdog whose response time is unbounded is a watchdog that cannot be certified1. The noise robustness data support real-world intent: accuracy stays at 96.04% at 10 dB SNR, 92.74% at 5 dB, and degrades smoothly rather than cliff-edged down to 71.26% at 0 dB (Fig. 14)1. And the class-level false negative rate, the metric that matters most when a missed fault is the expensive error, runs 0.29% to 8.29% across all 21 classes (Table IV)1.

Where a skeptic should push

The load-bearing assumption is that simulated waveforms at 33.3 kHz from one Boeing 787-inspired model are a faithful stand-in for the waveform population a real 400 Hz bus presents. Every accuracy figure in the paper inherits that assumption, and the authors themselves flag the sharpest version of the problem: because augmentation preceded the split, related samples can leak across train and test partitions, a known source of optimistic machine-learning estimates, and they name grouped parent-waveform partitioning and operating-condition-disjoint tests as future work1. Read this 96.94% as intra-distribution performance within one simulator's envelope, not generalization to aircraft power hardware, let alone to a different kind of power system entirely.

Second, the FPGA demo is an accelerator demo. The 93.77% CLB LUT utilization leaves almost no fabric for the data acquisition and STFT front ends the application actually requires; the authors note a representative STFT core needs 11,203 LUTs and argue most control logic could move to the ARM side of the MPSoC, but full integration with placement, routing and timing closure is untested1. Third, the GAN-generated 11.43% of the dataset and the augmented 85.71% were never validated against measured hardware waveforms, only against each other; spectral MSE of 10-9 shows the generator mimics its training data, not that either matches a physical bus. Fourth, the worst-class false negative rate of 8.29% (class 1, normal operation) is the number a certification authority would stare at hardest, because a watchdog that cries fault on normal operation 8 times in 100 gets switched off by its operators.

What a 400 Hz watchdog means for spacecraft buses

The non-obvious implication is that the monitoring stack has become smaller than the hardware it watches. A 175,685-parameter classifier at 15.52% DSP utilization means fault classification no longer needs a computing budget of its own; it can live as a tenant on the same FPGA or MPSoC that is already running the bus control loops, riding existing current and voltage sensing channels. For spacecraft PMAD, where every gram and watt of avionics is contested, that inverts the usual trade: instead of asking whether the health-monitoring algorithm fits the flight computer, the flight computer now has room to ask which power-quality questions are worth answering continuously, including questions nobody instrumented for, because retraining a model this size against a new anomaly class is cheap.

The threat is a data gap, not a compute gap. The paper's own related work is telling: the only public spacecraft-power fault corpus it can point to is NASA's Virtual Adapt simulation of the ADAPT testbed at Ames, which it criticizes as largely DC, while its cited spacecraft electrical-signal classification work runs on private datasets1. Aircraft at least have operating 400 Hz fleets to instrument; a deep-space bus has months of quiet cruise punctuated by anomalies almost nobody has labeled waveforms for. A monitoring model trained the way this one was, on simulator output augmented by its own generator, could look excellent in review and still be distributionally blind to the only events that matter, which is precisely the failure mode the authors' leakage caveat describes1.

The opportunity is to treat flight waveform capture as infrastructure. The architecture here, compact quantized classifier plus bounded-latency accelerator plus class-specific false negative budget, is exactly the shape a radiation-tolerant power controller would want, and its resource footprint (Tables V and VI) fits parts that already fly in processing roles1. What the field needs next is not a bigger network; it is a shared, waveform-level corpus of real spacecraft bus transients, on the aircraft side of this analogy the authors' IEEE DataPort release begins to sketch, so that the next 96.94% is measured against hardware reality rather than against a generator's imagination.

The bottom line

As simulation-based feasibility evidence, this is solid and unusually honest work: high confidence that a compact quantized network can classify a broad fault taxonomy on a 400 Hz bus with bounded latency in an accelerator, meaning the monitoring-compute barrier for power distribution systems is effectively gone. As evidence about real power systems, it is hypothesis, not result: no hardware bus, no disjoint validation, no flight waveform ever touched the pipeline. The claim that would change that is small and concrete, a parent-waveform-disjoint evaluation on an operating hardware testbed, plus waveform captures from a real 400 Hz system. If that confirms even 90% class accuracy with the same latency bounds, health monitoring for high-frequency power distribution, aircraft first and spacecraft close behind, becomes an integration problem rather than a research problem.

Frequently asked questions

Is this a flight-ready fault detector?

No. The power system is a simulation model inspired by the Boeing 787 architecture; the waveforms, including all test data, come from that model. The FPGA result is real hardware, but it is an accelerator evaluation: the network ran on a Xilinx ZCU102 board with the STFT front end computed on a host computer. Nothing has flown or been tested on a physical power bus.

Why 400 Hz instead of normal grid frequency?

Aircraft electrical systems run at 400 Hz because higher frequency allows smaller, lighter generators and transformers. The trade is that transients and disturbances have different spectral content than in 50 or 60 Hz grids, so models and datasets built for utility power do not transfer directly. This paper's central premise is that the 400 Hz regime needs its own training data and its own benchmarks.

How can accuracy be trusted if the test set is synthetic?

Only within stated limits. Augmentation and GAN synthesis were applied before the train, validation and test split, so test samples are held-out stochastic realizations from the same generation process, not independently acquired waveforms. The authors state this explicitly and name grouped parent-waveform partitioning as future work. The figures are best read as intra-distribution performance inside one simulator's envelope.

What does the FPGA implementation actually use?

Post-synthesis on the ZCU102: 391 of 2,520 DSP slices (15.52%), 581 of 912 Block RAM (63.71%) and 256,992 of 274,080 CLB LUTs (93.77%). The high LUT share reflects the generated DL processor logic; the authors note a representative STFT core would need about 11,203 more LUTs, leaving integration of the full sense-compute chain as future work.

How accurate is it under noisy measurements?

In simulation with added white Gaussian noise, the Compact ResNet holds 96.04% accuracy at 10 dB SNR, 95.25% at 7.5 dB, 92.74% at 5 dB, 86.55% at 2.5 dB and 71.26% at 0 dB, degrading smoothly rather than collapsing. These are controlled-noise simulation results, not hardware measurements.

Does the paper relate to spacecraft power at all?

Only indirectly. Its subject is aircraft. But its related work cites spacecraft electrical signal classification on private datasets and NASA's Virtual Adapt model of the ADAPT power testbed, and its monitoring architecture, compact quantized classifier with bounded latency on a shared FPGA, is the same shape a spacecraft bus manager would need. The spacecraft-specific evidence does not exist yet in this paper or, publicly, anywhere else cited by it.

References

  1. Guzman, I.C.; Babiceanu, R.; Pekoz, B. Deep Learning-Based Detection of Electrical Faults and Power Quality Disturbances in Aerospace Power Systems. IEEE Transactions on Aerospace and Electronic Systems, accepted September 2, 2026; arXiv:2609.10479 [eess.SP], September 9, 2026. https://arxiv.org/abs/2609.10479. Accessed 2026-10-10.